When a set of digital bits is transmitted from one device to another, noise in the channel may corrupt the bits and produce wrong bits to the receiving end. A coding process is thus needed to recover the wrong information. A certain number of extra bits, called parity bits, are added to the original bits by an encoder at the transmission end. The resulting new messages are called codeword. A decoder at the receiving end does the opposite, receiving the corrupted codeword and trying to recover the correct message bits based on what is received. This process of message recovery is called error-correction.
Different schemes have been proposed to set the constraints in the encoder/decoder pair in order to provide the highest possible success rate of error-correction. The set of constraints, usually represented by a parity check matrix, is called error-correction code (ECC). Low-Density-Parity-Check (LDPC) codes are a type of ECC that performs close to the theoretical limit.
A LDPC decoder uses iterative decoding algorithm, which is usually described by graph representations of the codes. The execution of the algorithm can be described as performing certain computations at the nodes of the graph and passing real messages along the edges, in both directions and iteratively. Iterative decoders have traditionally been implemented by digital circuits, however, research on analog decoding is getting attention because analog decoding consumes less power.
In analog implementations, each node in the graph acts as a computational module which communicates asynchronously with other nodes of the graph through edges. Iterations are thus eliminated and are replaced by the setting behavior of the system. Since the messages in the decoder are allowed to react with each other in a feedback asynchronous manner and do not have to wait for all messages to settle before the next decoding iteration can be started, the asynchronous iterative decoding has the advantage that its overall settling time is shorter relative to its discrete-time counterpart.
The architecture of an analog continuous-time iterative decoder for LDPC codes using the min-sum (MS) algorithm suitable for conventional CMOS circuit implementation has been proposed. See S. Hemati, A. H. Banihashemi, and C. Plett, “A 0.18-um CMOS Analog Min-Sum Iterative Decoder for a (32, 8) Low-Density Parity-Check (LDPC) Code,” IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2531-2540, November 2006. The decoder takes advantage of that MS decoding, featured by the minimum and summation operations and can be implemented easily by current-mode circuits. The system can be represented by a bipartite graph (called the Tanner graph) consisting of two classes of “nodes”: the variable nodes and the check nodes, separated by analog switches.
However, Hemati et al. does not provide a suitable interface for the analog input bits, which are usually represented in voltages. Moreover, the decoding time depends on the received codeword. The worst-case decoding time for very noisy received codewords can be a hundred times longer than those that are already correct when received. Thus, the decoding period is primarily determined by the worst-case decoding time for very noisy, but correctable, received codewords. This implies that, for most received codewords, even when the decoding result is acceptable, the iterative decoder still keeps running. A lot of power is wasted while the whole receiving end awaits the final results of the decoder. Hence, it is desirable to put an iterative decoder into a stand-by mode as soon as the decoding process is completed so that decoding time and power consumption can be greatly reduced.